Forecasts the physical qubit count, gate depth, and ancilla requirements for a target circuit before committing to hardware time — so teams can assess feasibility before it becomes a scheduling problem.
Quantum hardware time is scarce and expensive. Scheduling a circuit that exceeds the available qubit count, or that requires more gate layers than the device's coherence time allows, wastes that time — and may produce results too corrupted to use. The physical resource estimator runs these feasibility checks before any hardware commitment.
Given a circuit and its error correction allocation, the estimator calculates how many physical qubits are needed to support the required logical qubits at the target fidelity, how many gate layers the compiled circuit will require, how many ancilla and magic-state qubits the error correction overhead demands, and whether those totals fit within a specified hardware capacity. The estimator is aware of the φCoherent error-correction code structure and uses it to produce accurate overhead forecasts rather than worst-case bounds.
Calculates how many physical qubits are needed to encode the required logical qubits at the target error rate, accounting for the specific QEC code in use. The result reflects actual φCoherent code overhead, not a generic worst-case assumption.
Forecasts the total circuit depth after transpilation and error correction overhead, checking against hardware coherence time limits. Depth projections account for parallelization opportunities identified during transpilation.
Estimates the ancilla qubits and factory overhead required to supply the T-state gates needed by the circuit. Magic state distillation is often the dominant qubit cost in fault-tolerant circuits; the estimator surfaces this early.
Compares all estimated requirements against a provided hardware capacity specification and returns a pass or fail with actionable detail on which constraints are binding — qubit count, depth limit, or connectivity — so the team knows exactly what to address.
Pre-flight planning layer — run before scheduling hardware time. The error budget allocator's output feeds directly into the estimator. Both feed into the unified budget pipeline, which combines them in a single end-to-end pass. Use the estimator whenever a circuit's hardware requirements are unknown or a new hardware platform is being evaluated.
Provides the per-gate error allocation that drives the resource calculation, ensuring qubit overhead forecasts reflect actual criticality weighting.
Combines resource estimation and error budgeting in one workflow, eliminating the need to coordinate their outputs manually.
Published under the GNU AGPLv3 with whitepaper and reference implementation. Commercial licensing is available for closed-source deployments.