Converts logical circuits into hardware-ready circuits that respect each device's native gates, qubit connectivity, and QEC layout requirements — the bridge between what a circuit says and what hardware can execute.
Every quantum device has constraints that abstract circuits ignore: only certain gate types are natively supported; qubits can only interact with their physical neighbors; error correction requires specific qubit layout patterns. A circuit that ignores these constraints simply cannot run.
The transpiler is a three-stage pipeline — gate decomposition, qubit routing, and optimization — that transforms any logical circuit into one that satisfies all target hardware constraints. It is aware of the φCoherent error-correction layout requirements and can produce circuits specifically designed to minimize overhead when error correction is active.
Rewrites circuits that use non-native gate types into equivalent sequences of gates the target device natively supports, without changing what the circuit computes.
Inserts the additional operations needed to work around limited qubit connectivity, using a proven routing algorithm that keeps the added overhead to a minimum.
Reduces gate count and circuit depth after routing without changing outcomes. Fewer gates means fewer opportunities for errors, lowering the effective error rate for the same computation.
When error correction is in use, applies a Fibonacci-structured qubit assignment that minimizes the overhead of syndrome measurement circuits — the specialized operations that continuously check for errors during execution.
Checks all 7 non-trivial combinations of the three discrete symmetries — charge conjugation (C), parity (P), and time reversal (T) — for any circuit. Reports a per-check residual and optimal phase, identifying whether each symmetry holds to machine precision. T-gate circuits are correctly identified as CPT-asymmetric; Clifford circuits (real, Hermitian gates) pass all 7 checks. The 7-check count follows from the tribonacci-3 combinatorial structure: 2³ − 1 non-trivial subsets of {C, P, T}.
ZYZ Euler decomposition error < 3.1e-16 (machine precision) for Ry, Rx, and compound rotations. SABRE routing: 8q in 0.061 ms, 16q in 0.096 ms, 64q in 2.347 ms. Fibonacci qubit layout (logical k → physical F(k)): reduces SWAP overhead for QEC-structured circuits with Fibonacci interaction patterns. IBM heavy-hex 16q routing: 0.057 ms. All-to-all (IonQ) topology produces zero SWAPs, validating the routing engine. Qiskit transpiler: Python overhead adds 50–500 ms for equivalent circuits; phi-coherent: sub-3 ms, header-only C++, no subprocess.
Provides the target device's native gate set, qubit topology, and connectivity constraints that inform transpiler decisions.
Defines the qubit layout requirements that the transpiler's Fibonacci QEC layout stage is designed to satisfy.
Published under the GNU AGPLv3 with whitepaper and reference implementation. Commercial licensing is available for closed-source deployments.